Ateneo - UPO

In-depth study of the architecture of a modern computing system through the analysis of the RISC-V Instruction Set Architecture (ISA). The course explores the RISC-V machine language in detail, focusing on instruction types, formats, addressing modes, and procedure calls. Subsequently, it introduces advanced performance optimization techniques in processors, including branch prediction, out-of-order execution, and speculative execution, with specific attention to their integration into the pipeline. Finally, the course presents cache memory.

David A. Patterson, John L. Hennessy: Computer Organization and Design – RISC-V Edition, Second Edition, Morgan Kaufmann / Elsevier, 2020.

The goal of this module is to acquire a solid understanding of the RISC-V machine language, including instruction types, formats, addressing modes, and procedure call mechanisms. A second objective is to analyze major processor performance optimization techniques, such as branch prediction, speculative execution, and out-of-order execution, in the context of pipeline architectures. The module also introduces cache memory.

Knowledge of the concepts studied in module 1.

The topics covered in the course are mainly presented through lectures. Some concepts (e.g., instruction encoding in RISC-V, pipeline dependencies) are further explored through guided exercises. Throughout the course, exercises will be assigned for individual work to test learning progress and stimulate critical thinking. Group tutorials will complement the lectures with collaborative exercises.

On the DIR platform are available: electronic copies of lecture slides, a selection of sample exam questions, RISC-V ISA and pipeline-related exercises, general information about the course, and announcements concerning the course and examinations. Students with disabilities, Learning Disabilities (LD), or Special Educational Needs (SEN) may request specific services and tools by contacting the "Staff Sviluppo e Coordinamento Carriere e Servizi alle Studentesse e agli Studenti" and by consulting the dedicated page on the university website: https://www.uniupo.it/en/services/services-students-physical-or-learning-disabilities. Once they have contacted the University Staff, students may also get in touch with the course instructor to define examination accommodations concerning academic matters.

The assessment is carried out through a written exam. The test includes some questions, each of which may be structured into multiple parts. The questions may also include exercises aimed at evaluating the ability to apply theoretical concepts to practical cases. Each question is assigned a maximum score (typically from 3 to 5 points). Evaluation takes into account both correctness and completeness. A passing grade is achieved by demonstrating understanding and correct application of the core concepts addressed in each question. The final grade is the sum of the scores obtained in all questions.

Study of the RISC-V Instruction Set Architecture (ISA): instruction types, instruction formats, addressing modes, procedure calls. Analysis of processor performance optimization techniques: branch prediction, out-of-order execution, speculative execution. Study of how these techniques are integrated into the pipeline. Introduction to cache memory.

Be able to describe the features of the RISC-V machine language, with a focus on instruction types, formats, and addressing modes. Be able to explain the mechanism of procedure calls in RISC-V. Understand the main execution optimization techniques (branch prediction, out-of-order execution, speculative execution) and their impact on pipeline performance. Understand how memory cache works.