Ateneo - UPO

The layered architecture of modern computers is introduced. The main hardware components are presented and their interface towards the upper software layers is explained. The course comprises two units: the first one introduces the basic concepts, in particular the binary representation of data (numbers, text, images, analog quantities); the basic hardware components of a computer, in particular the processor architecture; the interaction between the processor, the memory and the main I/O devices. The second unit analyzes in detail a processor architecture, which is relatively simple but realistic, including its Instruction Set Architecture which is implemented through a microinterpreter; alternative internal organizations of the processor are discussed and their efficiency is compared; the basic principles about the cache memory and in general about the memory hierarchy of a computer system are introduced; finally the Instruction Set Architecture (ISA) level is introduced, with the analysis of the main characteristics of machine languages and the possible interaction modes between the processor and the I/O devices.

A.S. Tanenbaum, T. Austin: "Structured Computer Organization", VI Ed., Pearson Education, 2013.

One objective of this course is to set the basic knowledge on the high level structure of a computer, introducing its components and allowing to understand the basic operational principles and the interactions among such components, which are based on the binary encoding of any data type stored and processed by a computer. An important concept introduced by this course is that of layered architecture: the goal is to help understanding how complex functions can be implemented by composing simpler functions which can be realized in hardware or in software (applying the method of decomposing a complex problem in simpler subproblems).
Another important goal is to help understanding the impact of technological advances on the computer organization evolution; reasoning on this topic contributes developing the ability to compare the characteristics of different computer architecture (or computer component) organizations and to evaluate the differences in cost and performance.
Going into some detail, the course allows to acquire knowledge on the internal architecture of a processor, the optimization techniques, the main features of the machine languages, and how memory hierarchy works; in order to be aligned with the more recent architectural developments, some basic concepts on the main types of parallel architectures, and the problems related with the memory management and the impact on the programming style are presented.
Finally, during the course, the development of skills for autonomous learning of the latest advances concerning computer systems architecture is encouraged (in particular skills to search the necessary documentation on-line).

The course is introductory, so there are no specific requirements. The first unit should be studied before proceeding to the second one.

The topics of the course are mainly presented through class lectures that may be integrated with practical exercises based on various software tools with the aim of allowing to observe through examples the concepts presented in the lectures. After presenting each topic the students are challenged with exercises and formative quizzes. Tutored meetings in small groups are proposed, to develop and discuss exercises (similar to those included in the written exam).

It is possible to download electronic copy of all slides of the lectures, perform self-assessment on-line tests or exercises, the emulator of the MIC1 architecture, the associated micro-interpreter of IJVM and some programming examples. It is possible to find general information on the course and news about the lectures and the exam organization on the e-learning platform DIR. Specific forums can be used by students to ask questions on course topics or exercises, or to provide answers posted by other students.
Students with physical disabilities, Learning Disabilities or Special Education Needs can request specific services and tools via the "Staff Sviluppo e Coordinamento Carriere e Servizi alle Studentesse e agli Studenti", consulting the University webpage: https://www.uniupo.it/en/services/services-students-physical-or-learning-disabilities. Students with disabilities, learning disabilities or special education needs, once they have contacted the University Staff, can refer to the tutor in charge of the course to define the examination modalities, concerning academic aspects.

The exam is composed by two tests, one for each unit. The tests are written, but an oral integration may be required (for instance this could be the case when the written test grade is not fully sufficient, and the oral integration may allow to improve the grade and pass the exam). Intermediate tests can be organized (as a facilitation to pass the exam early at the end of the course) that may comprise lab exercises. The test includes four to six questions each of which possibly structured into several points. The questions may also take the form of exercises testing the ability to apply the learned concepts to practical examples.
Each unit has its own exam, and a sufficient final result is required in each unit in order to pass the exam of the whole course. The final grade is agreed upon by the teachers of the two units, taking into account the final result obtained in each one.

This course doesn’t have specific prerequisites. The first unit starts with a brief review of the historical evolution of computers, highlighting the impact that some technological advances had on the evolution from each generation to the next one. Then the basic terminology needed to dive into the details of the internal layered organization of modern computers is introduced; in particular the CPU (Central Processing Unit), the central memory and the I/O devices are described at an high level. The binary encoding of natural, integer and fractional numbers as well as text, images and analog quantities is defined. The combinatorial and sequential logical circuits are then introduced, after having presented the Boolean algebra, showing the correspondence between any Boolean expression and circuits composed of logical gates. Examples of common circuits are discussed and their use within the processor is explained. The interaction modes among the computer components are also described (including some examples of bus protocols).
The second unit builds on the concepts introduced in the first one and develops the details of a microprogrammed processor structure (whose basic components are presented in the first unit) showing how its machine language can be implemented through a microinterpreter based on the elementary operations of a simple but realistic hardware architecture. Possible variations on the theme of this first architecture are then discussed, each one introducing new performance improvements, following a path that resembles the evolution of modern processors. This step-by-step approach allows to introduce the pipeline-based architectures (complemented with hints on further improvements through techniques as branch prediction, speculative and out-of-order execution). The performance gap between the speed of CPU and central memory is also discussed, leading to the introduction of the cache memory (with its variants) and studying its effectiveness based on the concepts of temporal and spatial locality. Next an overview on the features of machine languages (the so called Instruction Set Architecture - ISA) is proposed, including the classification in CISC, RISC or Load/Store ISA. The virtual memory technique is also introduced, in the framework of the memory hierarchy. Finally some examples of parallel architectures are presented, discussing the problem of cache coherence in multiprocessors.

Unit 1: Describe the historical evolution of computers highlighting the impact of technology on their organization. Know the the positional representation of numbers in any base r (both integer and fractional numbers). Describe and apply the procedures for transforming an integer or a fractional number from decimal to base 2, 8 or 16 and viceversa. Be able to distinguish and derive the different encodings of signed integer numbers. Know and acquire the ability to apply the procedure to transform a fractional number into the floating point representation according to standard IEEE 754. Enunciate and explain the main Boolean algebra laws. Know how to represent a Boolean function in the two classical normal forms (sum of products or product of sums) and be able to apply simplification procedures (e.g. through the Karnaugh maps). Know the truth table of the main logical gates. Know how to derive a logic circuit implementing a given Boolean function. Be able to derive the Boolean function corresponding to a given circuit. Recognize a few common combinatorial and sequential circuits and describe the function(s) they implement. Describe the main components of a computer system and of the CPU, explain which are their characteristics, the operational behavior and the interaction modes. In particular describe the CPU and the fetch-decode-execute cycle, the difference between CISC and RISC architectures end the idea behand the pipeline based architectures. Describe the MIC1 architecture and the microinstructions language and explain which state change is caused by executing each microistruction.
Unit 2:
Describe how
an instruction is executed in MIC1 and analyze the techniques allowing to improve performance.
Acquire the ability to develop short programs in machine language (IJVM) and to extend the micro-interpreter with the introduction of new instructions.
Know the main characteristics of a machine language (e.g., instruction types, instruction formats, addressing modes). Understand the characteristics and the differences of the ISA in the CISC, RICS and load/store architectures.
Know the basic concepts behind the memory hierarchy, and understand the relevance of spatial locality and temporal locality principles in this context. Acquire the ability to explain and apply the operational techniques of the cache between CPU and central memory and of the virtual memory between central memory and secondary memory. Understand the difference between (virtual) address space and (physical) memory location and the related mapping techniques.
Achieve the capability to orienteering and autonomously learning the new trends about parallel architectures.