Ateneo - UPO

Continuation of the investigation of the computing architectures, organized as a layered set of virtual machines.
This module describes how to use the hardware components addressed in Module I to design MIC1, a microprogrammed processor (not real but plausible) with its language MAL.
Moreover, it analyses how to implement the IJVM machine language, derived from the Java bytecode Virtual machine, on the MIC1 architecture, by means of a micro-interpreter written in MAL. Different versions of MIC1/IJVM architecture are illustrated with progressively better performances. In addition, various process optimization techniques are illustrated (pipelines, jump prediction mechanisms, out of order execution, cache memories).
The following is a general overview of the Set Architecture (ISA) instruction level, with the analysis of the main characteristics of machine languages and the description of the load/store processors.
In addition, the module introduces operating system layer and the concept of virtual memory in the context of the hierarchy of memories in a computing architecture: in particular, the analogies and the differences with the cache are addressed.

A.S. Tanenbaum, T.Austin: "Computer Architecture: a structural approach", VI Edizione, Pearson Education Italia, 2013.

The goal of this module is to acquire knowledge about the internal organization of a processor and some architectural variants (e.g., pipeline, jump prediction, out-of-order execution, cache memories) can significantly change the speed of execution; understand how to distinguish between microprogrammed architectures and architectures that execute machine language instructions directly in hardware.
A second objective of the module is to learn the general characteristics of a machine language (types of instructions, instruction format, addressing methods) and discuss motivations, advantages, and disadvantages of different choices.
Finally, the module is intended to provide the knowledge to understand the virtual memory technique by placing it within the hierarchy of memories and by analyzing its implementation according to the paging technique.

Knowledge of topics studied in module 1

The topics covered in the course are mainly exposed through lectures
Some topics (e.g., MAL characteristics and programming, IJVM characteristics and programming, the behavior of MIC1 micro-interpreter for IJVM) are exemplified by means of experimentation through an emulator of the MIC1 architecture and of the associated IJVM micro-interpreter.
During the course, some exercises are submitted to be developed autonomously by students to verify their level of learning and stimulate a critical spirit, through the development of original and/or alternative solutions.
The course is complemented by a tutoring class in which some exercises will be proposed and developed in group.

On the DIR platform are available: the electronic copy of the slides used in the lectures, a selection of examples of exam texts, the emulator of the MIC1 architecture the associated micro-interpreter of IJVM and some MAL and IJVM programming examples, general information on the course and notices related to the course and exams.

The assessment of learning is carried out in written form. It is possible to request an oral supplement, for example if the vote is almost sufficient.
The test includes four to six questions, each of which can be structured in multiple points. The questions can also take the form of exercises to evaluate the ability to apply the theoretical concepts learned in the course to practical examples.
Each question is assigned a maximum grade (generally from 5 to 7). The evaluation considers the correctness of the answer and the level of completeness. A sufficient score is obtained if the student demonstrates that he has learned and knows how to apply the key elements addressed by the question.
The final grade for the learning assessment of contents addressed by this module is the sum of the marks obtained in each question.

Refinement of the description of the layered architecture introduced in module I: hardware level, micro-architecture level, Instruction Set Architecture level, Operating System level, Assembler programming level.
Analysis of MIC1 and of MAL, the related programming language, as an example of a microprogrammed architecture.
Description of the implementation of IJVM, derived from the Java bytecode Virtual machine, on MIC1 by means of a micro-interpreter implemented in MAL.
Exercises on MAL and IJVM programming and execution by means of a MIC-1 emulator equipped with a IJVM compiler and micro-interpreter.
Investigation of techniques to improve performance, by means of the introduction of a fetch unit and pipeline: analysis of their adoption in MIC2, MIC3 and MIC4 architectures.
Optimization techniques to improve performance: jump prediction, out-of-order execution, cache memories.
Characteristics of machine languages ​​(Instruction Set Architecture): data types, types of instructions, instruction format, addressing mode, handling of procedure calls. Characteristics of load/store machine ISA. Analysis of solutions for interaction among CPU and Input / Output devices.
Analysis and comparison of architectures and machine languages ​​of real processors.
Introduction to virtual memory, in the context of memory hierarchy: comparison with the cache, and in-depth analysis on virtual memory based on paging technique.

Explain the organization of a micro-processor and its main functional units.
Describe how it is performed
an instruction in this type of machine know analysis the techniques to improve performance.
Be able to perform the conversion from the symbolic representation of machine language instructions, oriented to programming, to the binary format inside the machine.
Be able to develop short programs in machine language (MAL and IJVM) and to extend the micro-interpreter with the introduction of new instructions.
Know the main characteristics of a machine language (e.g., instruction types, instruction formats, addressing modes).
Understand the characteristics and the differences of the ISA in the CISC, RISC and load/store architectures.
Achieve the necessary skills to analyze and compare existing machine languages.
Know the use of the memory hierarchy, by understanding the relevance of spatial locality and temporal locality principles. To be able to apply the technique of cache between CPU and RAM and of virtual memory between RAM and secondary memory. To understand the difference between (virtual) address space and (physical) memory location and the related mapping techniques.