Ateneo - UPO

The architecture of modern computers is introduced emphasizing its layered structure. The main hardware components are presented and their interface towards the upper software layers is explained.
This is the first of two units that together constitute one integrated course. It lays out the basis by introducing: the binary encoding of all data types (numbers, text, images, analog quantities), the basic hardware components of a computer and in particular the internal structure of the CPU, the interaction between the CPU and the central memory and between the CPU and the I/O devices.
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Continuation of the investigation of the computing architectures, organized as a layered set of virtual machines.
This module details the structure of MIC1, a microprogrammed processor (not real but plausible, introduced in module I) through the analysis of a micro-interpreter of IJVM machine language, derived from the Java bytecode Virtual machine. Different versions of the microarchitecture are illustrated with progressively better performances. In addition, various process optimization techniques are illustrated (pipelines, jump prediction mechanisms, out of order execution, cache memories).
The following is a general overview of the Set Architecture (ISA) instruction level, with the analysis of the main characteristics of machine languages and the description of the load/store processors.
In addition, the module introduces operating system layer and the concept of virtual memory in the context of the hierarchy of memories in a computing architecture: in particular, the analogies and the differences with the cache are addressed.
Finally, an overview of parallel architectures is presented, with some details on the issues related to the coherence of cache memories in multi-processor architectures.

A.S. Tanenbaum, T. Austin: "Structured Computer Organization", VI Ed.,
Pearson Education, 2013.
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A.S. Tanenbaum, T.Austin: "Computer Architecture: a structural
approach", VI Edizione, Pearson Education Italia, 2013.

The first goal of this course is to develop the knowledge on the basic concepts of binary information encoding (binary representation of numbers, text and images) and of the processing of binary data through logical functions, defined by means of Boolean algebra, and implemented by logic circuits.
Another goal is to develop the knowledge about the main components of a computer, and understand the basic operational principles and the interactions between such components; in this context it is interesting to highlight the impact that the technological advances have on the organization of computer architecture. Such observations allow to exercise the ability to compare the characteristics of different computer architecture organizations (or of different computer component organizations) and to evaluate the differences in cost and performance.
Another important concept introduced in this course is the layered structure of the computer systems: it derives from the application of the method of problem decomposition into simpler sub-problems. To help understanding in practice such concept, it is exemplified by presenting the architecture of a simple processor (MIC1, not real but realistic): building on the simple operations that can be executed directly by the basic hardware architecture, it is possible to implement the more powerful MIC1 machine language (IJVM) through microprogramming, the latter topic is developed in the second module.
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The goal of this module is to acquire knowledge about the internal organization of a processor and some architectural variants (e.g., pipeline, jump prediction, out-of-order execution, cache memories) can significantly change the speed of execution; understand how to distinguish between microprogrammed architectures and architectures that execute machine language instructions directly in hardware.
A second objective of the module is to learn the general characteristics of a machine language (types of instructions, instruction format, addressing modes) and discuss motivations, advantages and disadvantages of different choices.
Moreover, the module is intended to provide the knowledge to understand the virtual memory technique by placing it within the hierarchy of memories and by analyzing its implementation according to the paging technique.
Finally, the module aims to provide basic knowledge about the main types of parallel architectures and understand the main impact on the memory management and issues on programming.

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Knowledge of topics studied in module 1

The topics of the course are mainly presented through class lectures that may be integrated with lab sessions (to experiment the internal representation of various data types, to design and simulate combinatorial and sequential circuits, to experiment the execution of simple machine language programs through an emulator).
During the lectures an interactive tool (Wooclap) is used to get a feedback from the students through anonymous quizzes that can be answered using the smartphone. This way the students are stimulated to reflect; moreover this activity allows an early detection of the possible critical aspects in the learning process.

After presenting each topic the students are challenged with exercises and formative quizzes. Tutored meetings in small groups are proposed, to develop and discuss exercises (similar to those included in the written exam).
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The topics covered in the course are mainly exposed through lectures
Some topics (e.g., IJVM characteristics and programming, the behavior of MIC1 micro-interpreter for IJVM) are exemplified by means of experimentation through an emulator of the MIC1 architecture and of the associated IJVM micro-interpreter.
During the course, some exercises are submitted to be developed autonomously by students to verify their level of learning and stimulate a critical spirit, through the development of original and/or alternative solutions.
The course is complemented by a tutoring class in which some exercises will be proposed and developed in group.

It is possible to download electronic copy of all slides of the lectures, perform self-assessment tests, read general information on the course and news about the lectures and the exam organization on the e-learning platform DIR .
General information on the organization of the course and of the exams are published through a forum. Specific forums can be used by students to ask questions on course topics or exercises, or to provide answers posted by other students.
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On the DIR platform are available: the electronic copy of the slides used in the lectures, a selection of examples of exam texts, the emulator of the MIC1 architecture the associated micro-interpreter of IJVM and some programming examples, general information on the course and notices related to the course and exams.

The examination can be either oral or a written test (usually it is written in the first exams session, while it may be oral in the other sessions with a few enrolled students). When the exam takes the form of a written test, it is possible to ask for an oral integration (for instance this could be the case when the written test grade is not fully sufficient, it is possible to ask for an oral integration to improve the grade to pass the exam). Intermediate tests can be organized (as a facilitation to pass the exam early at the end of the course) that may comprise lab exercises. The test includes four to six questions each of which possibly structured into several points. The questions may also take the form of an exercise testing the ability to apply the learned concepts to practical examples. The threshold to pass the exam is the 60% of the global sum of points assigned to the questions.
Each unit has its own exam, and a sufficient final result is required in each unit in order to pass the exam of the whole course. The final grade is agreed upon by the teachers of the two units, taking into account the final result obtained in each one.
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The assessment of learning is carried out in written form. It is possible to request an oral supplement, for example if the vote is almost sufficient.
The test includes four to six questions, each of which is, in general, structured in multiple points. The questions can also take the form of exercises to evaluate the ability to apply the theoretical concepts learned in the course to practical examples.
Each question is assigned a maximum grade (generally from 5 to 7). The evaluation considers the correctness of the answer and the level of completeness. A sufficient score is obtained if the student demonstrates that he has learned and knows how to apply the key elements addressed by the question.
The final grade for the learning assessment of contents addressed by this module is the sum of the marks obtained in each question.

Brief review of the historical evolution of computers (from Charles Babbage’s Analytical Engine up to current computers).Information encoding: binary encoding of integer numbers, both unsigned and signed. Transformation from binary to octal and hexadecimal representation and viceversa. Arithmetic operations with binary numbers. Encoding of the fractional numbers: fixed point and floating point (according to IEEE 754 standard). Text encoding (ASCII, Unicode, UTF-8). Redundant codes for error detection and correction. Images encoding (bitmap, image resolution and depth).Boolean algebra, AND, OR, NOT, NAND, NOR gates. From logical functions to combinatorial circuits (truth tables, sum of products and product of sums normal form expressions, simplification by means of algebra laws, or through Karnaugh’s maps). Examples of circuits: Decoder, Multiplexer, Half Adder, Full Adder, ALU, etc. Sequential circuits: Latch, Flip-flop, registers and memories. Main components of a computer (CPU, RAM memory, Magnetic disks, RAID, Optical disks, BUS, various peripherals) and their basic operating principles. Central Processing Unit: fetch-decode-execute cycle. CISC and RISC processors, Processors with pipeline architecture. Introduction the MIC1 architecture (see textbook).
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Refinement of the description of the layered architecture introduced in module I: hardware level, micro-architecture level, Instruction Set Architecture level, Operating System level, Assembler programming level.
Investigation of an example of microprogrammed architecture that executes IJVM, derived from the Java bytecode Virtual machine, on MIC1 architecture introduced in module I, by means of a micro-interpreter implemented in MAL.
Exercises on IJVM programming and executions by means of a MIC-1 emulator equipped with a IJVM compiler and micro-interpreter.
Investigation of techniques to improve performance, by means of the introduction of a fetch unit and pipeline: analysis of their adoption in MIC2, MIC3 and MIC4 architectures.
Optimization techniques to improve performance: jump prediction, out-of-order execution, cache memories.
Characteristics of machine languages ​​(Instruction Set Architecture): data types, types of instructions, instruction format, addressing mode, handling of procedure calls. Characteristics of load/store machine ISA. Analysis of solutions for interaction among CPU and Input / Output devices.
Analysis and comparison of architectures and machine languages ​​of real processors.
Introduction to virtual memory, in the context of memory hierarchy: comparison with the cache, and in-depth analysis on virtual memory based on paging technique.
Description of some types of parallel architectures, and analysis of issues related to coherence of cache memories in multi-processor architectures.

Describe the historical evolution of computers highlighting the impact of technology on their organization. Explain the positional representation of
numbers in any base r (both integer and fractional numbers). Describe and apply the procedures for transforming a fractional number from decimal to base 2, 8 or 16 and viceversa. Describe and apply the procedure to obtain the binary encoding of signed integers in the two representation: sign and modulus or two’s complement. Execute arithmetic operation with binary numbers. Describe and apply the procedure to transform a fractional number into the floating point representation according to standard IEEE 754. Enunciate and explain the main Boolean algebra laws. Represent a Boolean function in different form (SP and PS normal forms, and simplified either applying algebraic rules or through Karnaugh maps). Derive a logical circuit for a given Boolean algebra expression. Given a circuit, state which Boolean function it implements. Recognize the basic combinatorial and sequential circuits and describe the function they implement. Describe the main components of a computer, list the main characteristics, how they work and how they interact. In particular describe the CPU main components and the fetch-decode-execute cycle. State the differences between CISC and RISC architectures and the principle behind the pipeline architectures. Describe the microinstructions language of MIC1 (both in binary and mnemonic representation), implement some simple microprograms using such language and simulate their execution.
Acquire the skills for autonomous learning specific aspects or more advanced topics about computer architecture (in particular skills to search the necessary documentation on-line).
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Explain the organization of a micro-processor and its main functional units.
Describe how it is performed an instruction in this type of machine know analysis the techniques to improve performance.
Be able to perform the conversion from the symbolic representation of machine language instructions, oriented to programming, to the binary format inside the machine.
Be able to develop short programs in machine language (MAL and IJVM) and to extend the micro-interpreter with the introduction of new instructions.
Know the main characteristics of a machine language (e.g., instruction types, instruction formats, addressing modes).
Understand the characteristics and the differences of the ISA in the CISC, RISC and load/store architectures. Achieve the necessary skills to analyze and compare existing machine languages.
Know the use of the memory hierarchy, by understanding the relevance of spatial locality and temporal locality principles. To be able to apply the
technique of cache between CPU and RAM and of virtual memory between RAM and secondary memory. To understand the difference between (virtual) address space and (physical) memory location and the related mapping techniques.