Ateneo - UPO

The course provides an in-depth study of modern computer architecture, focusing on microarchitecture organization and machine language, with particular emphasis on the RISC-V Instruction Set Architecture (ISA).The course topics are organized into the following main modules:Structural Approach and Levels of Abstraction: The concept of the virtual machine and the conventional hierarchy of computer abstraction levels (from L0 to L5). Analysis of the semantic gap between high-level programming languages and hardwired hardware. Inter-level execution techniques: translation and interpretation.The RISC-V Instruction Set Architecture (ISA): Philosophy and taxonomy of RISC architectures. Systematic study of the 32-bit base instruction set (RV32I) and the extensions for integer multiplication and division (RV32IM). Structural analysis of instruction formats (R, I, S, B, U, and J).Assembly Programming and ABI Conventions: Syntax and semantics of arithmetic and logical instructions, data transfer operations (load/store), and control flow instructions (conditional and unconditional branches). Procedure and function management, including the Application Binary Interface (ABI) conventions for register usage, routine invocation, and stack frame allocation/deallocation. Introduction to interfacing with input/output peripherals using software simulators.Single-Cycle Processor Organization: Structural modeling of the processor datapath and control unit for executing a subset of native instructions. Analysis of critical paths, execution timing, and the inherent performance scalability limitations of the single-cycle design.Microarchitecture and Pipelining: The concept of temporal parallelism as implemented in a standard five-stage pipeline (IF, ID, EX, MEM, WB). Identification and classification of pipeline hazards, including structural, data, and control hazards. Hardware techniques for hazard mitigation, including pipeline stalling, forwarding (bypassing) networks, and branch prediction strategies (static as well as dynamic 1-bit and 2-bit predictors).

Recommended Main Textbook:Patterson, David A., and John L. Hennessy. Computer Organization and Design RISC-V Edition: The Hardware Software InterfaceCourse Materials Provided by the Instructor: All supporting materials used during the lectures constitute an essential and integral part of the preparation for the examination. Specifically, these include:Lecture slides and supplementary lecture notes.Exercise sets and RISC-V Assembly programming simulations.Additional technical documentation.All course materials will be made available promptly and updated regularly through the University's e-learning platform (DIR) and via the institutional Google Drive folder shared with all student accounts.

The course is part of the foundational technological and infrastructural area of computer science. Its primary objective is to provide students with a rigorous and in-depth understanding of the internal organization of modern computing systems, bridging the semantic gap between high-level programming languages and the underlying hardwired hardware.Through a detailed study of the open-source RISC-V Instruction Set Architecture (ISA), the course aims to develop the methodological awareness required to evaluate the impact of hardware design choices on software performance.Specifically, the course is designed to achieve the following learning objectives:Understanding Abstraction: Develop a solid understanding of the computer as a hierarchy of virtual machines and conventional abstraction levels, analyzing the mechanisms of translation and interpretation across different levels.Mastery of the ISA and Assembly Programming: Develop the ability to analyze, encode, and implement low-level programs while rigorously applying the conventions of the Application Binary Interface (ABI) for register management, procedure calls, and stack frame organization.Microarchitecture Analysis: Understand the internal organization of a processor by critically analyzing the structural limitations of the single-cycle processor model and the performance benefits introduced by temporal parallelism through pipelining.Optimization and Hazard Resolution: Develop the ability to identify structural, data, and control hazards within a five-stage pipeline and to understand and quantitatively evaluate the effectiveness of both hardware and software mitigation techniques, including pipeline stalls, forwarding (bypassing) networks, and branch prediction.By the end of the course, students will have developed a solid engineering and computational mindset that is essential not only for understanding modern processor architectures, but also for designing optimized software, understanding operating systems, and interfacing with embedded systems.

To successfully follow this course, students are expected to possess a solid foundation in mathematics and computer science, preferably acquired during first-year coursework.

In particular, the following background knowledge is considered essential:

Fundamentals of Computer Architecture I:
Understanding of positional number systems (binary, octal, and hexadecimal) and the corresponding arithmetic conversion techniques.
Knowledge of data representation in memory, including two's complement representation for signed integers, the IEEE 754 standard for floating-point numbers, and character encoding schemes.
Familiarity with Boolean algebra and fundamental digital logic circuits, including logic gates, combinational circuits (such as multiplexers and decoders), and basic sequential circuits (such as flip-flops and registers).
Programming I:
Proficiency in structured programming principles and control flow constructs, including sequence, selection (conditional statements), and iteration (loops).
Familiarity with variables, memory allocation, pointers, elementary data structures (such as arrays), and code modularization through the definition and invocation of functions or procedures.
Prior knowledge of a high-level programming language that provides explicit memory management (e.g., the C programming language) is strongly recommended, as it facilitates understanding of how variables and registers are mapped at the Assembly level.

No formal background in electronics is required, as the processor will be studied exclusively from the perspective of its logical and functional architecture.

The course adopts an integrated teaching approach that combines rigorous theoretical instruction with a strong practical component. Its primary objective is to encourage students to play an active and critical role in the learning process.The course consists of the following teaching activities:Interactive lectures: The theoretical foundations of computer architecture—including the RISC-V Instruction Set Architecture (ISA), datapath organization, pipelined microarchitecture, and hazard management—will be presented through classroom lectures supported by multimedia presentations (slides). Lectures are designed to be highly interactive rather than one-way presentations, with students encouraged to participate through questions, open discussions, and the joint analysis of hardware design choices.Practical exercises and problem-solving sessions: A significant portion of the course is devoted to guided practical sessions focused on low-level programming in RISC-V Assembly and the application of the Application Binary Interface (ABI) conventions. During these activities, students will solve optimization and performance-analysis problems—such as evaluating clock cycles and pipeline stalls—working both individually and in small groups to promote collaborative learning and peer instruction.Use of software simulators: To translate theoretical concepts into practical skills, laboratory activities make extensive use of software simulators based on the RV32 architecture. These tools enable students to develop, test, and validate Assembly programs while observing the behavior of registers, memory, and input/output devices in real time.E-learning support and asynchronous interaction: The University's e-learning platform (DIR) and the institutionally shared Google Drive folder will serve not only as repositories for lecture slides, exercise sets, and supplementary notes, but also as collaborative learning environments. Students—including those who do not attend lectures regularly—will be able to comment on shared documents to request further explanations, raise questions, or initiate discussions, thereby maintaining an ongoing channel of interaction with the instructor throughout the course.

Student Office Hours: The instructor is continuously available to provide clarifications on course topics, review exercises, and discuss exam-related work. Office hours are held by appointment, to be arranged in advance via email (to: mirko.lai@uniupo.it). To ensure efficient handling of requests, students are kindly asked to use their institutional email address and to include the following subject line:COMPUTER ARCHITECTURE 2 25/26 [ALESSANDRIA / VERCELLI CAMPUS] (specifying their campus of affiliation). Meetings may take place either in person at the instructor’s office or online.Support for students with disabilities or Specific Learning Disorders (SLD): Students with disabilities, Specific Learning Disorders (SLD), or Special Educational Needs (SEN) may request dedicated services and support tools by contacting the Staff for Career Development and Student Services and by consulting the relevant page on the University website: https://uniupo.it/it/servizi/servizi-studentesse-e-studenti-condizione-di-disabilit%C3%A0-e-dsa. After contacting the University staff, students with disabilities, SLD, or SEN may also reach out to the course instructor regarding exam arrangements and teaching-related aspects.Active collaboration and error reporting: The teaching materials uploaded to the institutional Google Drive folder are configured to allow comments. Students (both attending and non-attending) are strongly encouraged to use this feature to request clarifications directly on the materials or to report any errors in slides or exercise sheets, thereby actively contributing to the continuous improvement of the course content.Course integration: This course is closely integrated with the Computer Architecture 1 module. Although the two modules may be attended and passed independently, students are strongly advised to approach Computer Architecture 2 only after having consolidated the concepts related to logic circuits and information representation covered in the first module.

The examination is designed to assess the achievement of the course learning objectives and intended learning outcomes. The assessment procedures are identical for both attending and non-attending students.1. Written Examination (Mandatory)Student assessment is primarily based on a written examination graded on a 30-point scale. The maximum score that can be obtained through the written examination is 26/30. To obtain a higher final grade, students must take the optional oral examination.The written examination is considered passed with a minimum score of 18/30 and is divided into two parts.Part I – Multiple-Choice Test (18–21 points)The first part consists of a 22-question multiple-choice test covering the entire course syllabus.Each correct answer is worth 1.1 points.Incorrect or unanswered questions receive 0 points (no negative marking).Students must answer at least 16 questions correctly to pass this part.The maximum score for this section is 21 points.Part II – Theory Questions and Exercises (22–26 points)Students who successfully complete the first part with at least 19 correct answers are admitted to the second part, which consists of five questions, including open-ended questions, short-answer questions, and/or problem-solving exercises.This section is intended to assess students' understanding of the theoretical concepts, their ability to apply the acquired knowledge, and their analytical and problem-solving skills. The maximum score obtainable in the written examination is 26/30.2. Optional Oral ExaminationStudents who obtain a score of 25/30 or 26/30 in the written examination may choose to take an optional oral examination.The oral examination consists of two reasoning-based questions and/or exercises designed to assess the student's ability to apply the concepts learned during the course to new situations. Students are expected to infer appropriate solutions from the underlying principles, even when the specific problem has not been explicitly addressed during the lectures.The outcome of the oral examination may result in a change of up to ±5 points to the final grade. Consequently, the written examination grade may either be increased (up to 30 cum laude, where warranted by the student's overall performance) or decreased. In the latter case, however, the final grade cannot be lower than 21/30.

The course provides a detailed and comprehensive study of the following topics, organized into five main modules.Module 1: The Structural Approach and Levels of AbstractionThe concepts of the virtual machine and hardware abstraction.The hierarchy of abstraction levels in modern computing systems, from the digital logic level (L0) to the application level (L5).The semantic gap between high-level programming languages and hardware circuits.Program execution across abstraction levels: compilation (translation) and interpretation. The fetch-decode-execute cycle.Module 2: The RISC-V Instruction Set Architecture (ISA)Design philosophy of Reduced Instruction Set Computer (RISC) architectures compared with Complex Instruction Set Computer (CISC) architectures.The RISC-V 32-bit base instruction set (RV32I), including the general-purpose registers (x0–x31) and the program counter.Introduction to the RV32IM extension for hardware-supported multiplication and division.Systematic study of the native instruction formats:R-type (arithmetic and logical instructions)I-type (immediate and load instructions)S-type (store instructions)B-type (conditional branches)U-type (upper immediate instructions)J-type (unconditional jumps)Instruction encoding and decoding techniques in binary and hexadecimal machine language.Module 3: Assembly Programming and ABI ConventionsSyntax, semantics, and addressing modes of RISC-V Assembly instructions:Arithmetic and logical operations (add, sub, and, or, xor, slt, and immediate variants).Data transfer instructions for memory access (lw, lh, lb, sw, sh, sb).Control-flow instructions, including unconditional jumps (jal, jalr) and conditional branches (beq, bne, blt, bge).The RISC-V Application Binary Interface (ABI): conventions for register allocation and preservation, including argument and return registers (a0–a7), temporary registers (t0–t6), and saved registers (s0–s11).Hardware and software management of procedures (functions), including the role of the Return Address register (ra) and the Stack Pointer (sp).Allocation, management, and deallocation of stack frames for nested and recursive function calls.Mapping high-level programming constructs (if-else statements, while and for loops, arrays, and pointers) into Assembly language.Module 4: CPU Organization: The Single-Cycle ProcessorOperating principles of a processor and the main datapath components: Instruction Memory, Register File, Arithmetic Logic Unit (ALU), Data Memory, and Sign Extension Unit.Design and operation of the Control Unit, including the generation of global and local control signals based on the instruction opcode and Funct3/Funct7 fields.Datapath analysis for the different instruction classes (R-type, Load, Store, and Branch).Performance analysis of the single-cycle processor, including critical path analysis, clock cycle computation, and the inherent scalability limitations of the single-cycle architecture.Module 5: Advanced Microarchitecture: Pipelining and Hazard ManagementTemporal parallelism and the organization of the classic five-stage pipeline:IF (Instruction Fetch)ID (Instruction Decode)EX (Execute)MEM (Memory Access)WB (Write Back)Pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB) and propagation of control signals.Pipeline performance analysis, including throughput, latency, and speedup evaluation.Pipeline hazards: classification and mitigation techniques.Structural hazards: causes and hardware solutions, including separate instruction and data memories.Data hazards: Read-After-Write (RAW) dependencies. Hazard mitigation techniques, including pipeline stalling (bubble insertion) through the Hazard Detection Unit and forwarding (bypassing) networks implemented by the Forwarding Unit. Analysis of the critical load-use data hazard and the mandatory stall.Control hazards: the impact of branch instructions on pipeline execution and pipeline flushing mechanisms.Hardware optimizations for branch instructions: early branch resolution during the Instruction Decode stage (fast equality comparison and branch target computation) and the resulting implications for data hazards.Branch prediction: static techniques (always taken/always not taken) and dynamic prediction. Structure and operation of the Branch History Table (BHT), including one-bit predictors, two-bit saturating predictors, and an introduction to correlated branch predictors.Hardware support for exceptions and interrupts, including the conceptual and operational differences between asynchronous interrupts and synchronous traps, CPU state preservation mechanisms, and transfer of control to the appropriate exception or interrupt handler.

The learning outcomes are defined according to the Dublin Descriptors and describe the competencies that students are expected to acquire by the end of the course.In particular, the course aims to develop:Knowledge and understanding: the ability to describe computer architecture, the RISC-V ISA, CPU operation (datapath and control unit), five-stage pipelines and their hazards, as well as distinguishing between traps and interrupts.Applying knowledge and understanding: the ability to translate programs into RISC-V Assembly, work with machine-level instructions, analyze the datapath and CPU performance, and solve pipeline and hazard-related problems using calculations and timing diagrams.Making judgements: the ability to evaluate trade-offs between different architectures, optimize Assembly code, and compare branch prediction strategies based on program behavior.Communication skills: the correct and rigorous use of technical terminology and the ability to clearly describe processor operation and its interaction with software.Learning skills: the development of an autonomous learning approach to study modern architectures (such as ARM and x86) and to connect acquired knowledge with subsequent courses, particularly Operating Systems and Embedded Systems.